Antenna Buffer Test

Purpose

This test exercises the antenna buffer, the firmware component that writes large snapshots of raw antenna voltages to DDR memory for them to be streamed over the 40GbE interface. This makes capturing multiple seconds of raw data possible without having to stream it “live” to MCCS or CSP. This test is predominantly a proof of concept for the antenna buffer, it will be extended in future to be a more thorough test.

NOTE: This test only operates on the first FPGA of the first TPM in a station.

NOTE: For data acquisition to function correctly, the network interfaces on the TPM must be working, as well as the link to the LMC destination. The LMC destination must be configured to route traffic to the server running the tests. For all tests the simplest option is for the CSP and LMC destinations to be the same network interface, routing all traffic to the server running the tests.

Methodology

  1. All firmware internal signal & pattern generators are reset and disabled.

  2. Integrated data and station beam transmission is stopped.

  3. JESD test pattern generator is started with an incrementing pattern, mocking the ADC output into the system.

  4. The antenna buffer DDR allocation is specified. For this test, this defaults to a 64MB circular buffer, beginning 512MB into the available DDR capacity.

  5. Antennas 0 and 1 are selected for use with the antenna buffer.

  6. Two JESD ramp patterns are enabled in the pattern generator

  7. DAQ receiver is configured and initialised with the required UDP port and network interface.

  8. A single shot snapshot of the contents of the antenna buffer is requested from the TPM.

  9. The received data is verified to match the ramp pattern for the two antennas as expected.

  10. The station beamformer is restarted if it was running before the test began.