F2F (FPGA to FPGA) Test

Purpose

This test verifies the link between the two FPGAs on a TPM. An internal test generator within both FPGAs is used to stream high speed data between the two FPGAs and verify no data is corrupted or lost. This test is executed on all FPGAs, on all TPMs, simultaneously for a specified duration.

Methodology

  1. A data pattern is selected based on the hardware version of TPM under test. This is provided to the F2F test component of the firmware.

  2. For all FPGAs in all TPMs, the internal F2F transmit (TX) test is started

  3. For all FPGAs in all TPMs, the internal F2F receive (RX) test is started

  4. The software will monitor the status of the internal test once per second and display continuous error counts and error locations, if detected.

  5. The test finishes either due to an error or due to the duration elapsing.