Synchronisation Test

Purpose

This test checks for errors in the pulse-per-second (PPS) signal provided to the TPMs. This verifies:

  • The PPS in use is externally provided

  • The PPS period is 1.0s as detected by TPM

  • The PPS phase does not differ by more than 1.25 ns between FPGAs on the same TPM

  • The PPS phase does not differ by more than 5.00 ns over time for a given TPM.

The test also saves to disk a CSV file of PPS period, PPS phase and TPM temperature. The test runs for a configurable amount of time, defaulting to 120 seconds.

Methodology

The following steps repeat once per second for each TPM. A failure of any checks will result in an error being logged and the test failing, however, the test will still continue for the configured duration.

  1. The PPS phase (pps delay) is read for both FPGA and verified to be equal or +/- 1 ADC sample (1.25 ns)

  2. The current PPS phase (pps delay) is used to update the historical minim and maxim for the test. If the difference between the minimum and maximum is more than 5ns then the test logs an error.

  3. For both FPGAs, the PPS is verified to be externally provided

  4. For both FPGAs, the PPS period is verified to be 1.0s

  5. A line is appended to a CSV log file with the current time, tile ID, PPS period, PPS phase and maxim PPS phase drift