SPEAD Antenna Buffer Test

Purpose

This test verifies the SPEAD header fields of the Antenna Buffer. The SPEAD packets are captured using the DAQ receiver. This test uses the SPEAD header metadata passed by the DAQ for verification. Given below is the SPEAD header specification which is verified in this test.

../../_images/antenna_buffer_spead_header.png

Antenna Buffer data is requested at 1 timestamp intervals. This corresponds to 864*512 samples of ADC data. Due to data being requested from each FPGA separately the test is run on one FPGA at a time.

Methodology

  1. Establish connection to the station and specified TPM(s).

  2. Sets up the Antenna Buffer, with the correct configration

  3. Configure and initialise the DAQ receiver with the required UDP port and network interface.

  4. Start the DAQ in Antenna Buffer data mode.

  5. Request Antenna Buffer data for a specific TPM and FPGA, choosing 1 or 2 randomly selected antennas.

  6. Wait for the DAQ to receive data.

  7. Extract the spead header fields from the data callback.

  8. Verify SPEAD header fields by comparing with the expected values.

  9. Repeat steps 4-8 for set number of iterations

  10. DAQ is then stopped, as the DAQ can only deal with a set number of tiles and antennas

  11. Repeat steps 4-10 for all tiles and FPGAs

  12. Stop the DAQ and clean up temporary directory.