Full Station Test

Purpose

This test verifies the performance of the tile and station beamformers by comparing offline beam power to realtime beam power. Channelized data from the TPMs is captured and software beamforming is used to calculate offline beam power, this is then compared to the realtime station beam power for this channel being sent to CSP. This test also aims to stress the system. Multiple background processes sharing the DDR memory in addition to the station beamformer are enabled. The beamformer can also optionally be enabled and disabled multiple times throughout the test.

NOTE: This test operates on all TPMs in a given station.

NOTE: For the station beamformer and data acquisition to function correctly, the 40GbE interfaces on all TPMs must be working as well as the link to the CSP and LMC destinations. The CSP and LMC destinations must both be configured to route traffic to the server running the tests. For all tests the simplest option is for the CSP and LMC destinations to be the same network interface, routing all traffic to the server running the tests.

NOTE: This test is currently only support when LMC data is transmitted to the test server over 40GbE (SDN). If LMC data is transmitted via 1GbE (NSDN) then the test will be skipped.

Methodology

  1. DAQ receiver is configured and initialised with the required UDP port and network interface.

  2. Firmware embedded DDR test and antenna buffer are started. This is to maximise competition for the DDR memory. The station beamformer is allocated the first 512MB of the DDR, the embedded DDR test the next 256MB and the antenna buffer the next 256MB.

  3. A calibration and time domain delays are applied to the antennas.

  4. An LMC snapshot of continuous channelised data for a specified channel is requested from all TPMs. This defaults to channel 4.

  5. The captured data is used to calculate offline beamformed channel power

  6. The station beam is acquired as realtime beamformed channel power and compared to the offline beamformed power with an expected tolerance.

  7. This process is repeated for different maximum time domain delays applied to the antennas. On each subsequent execution the max delay is halved (and rounded down). The default is eight test executions, beginning at a max delay of 128, then 64, then 32… down to 1.

  8. The background embedded DDR test is checked to see if any DDR errors were detected during the test.

  9. The embedded DDR test and antenna buffer are stopped.