C2C (Chip to Chip, FPGA to CPLD) Test

Purpose

This test is intended to verify communication between the software, the TPM’s CPLD and each of its TPM’s FPGAs. A TPM is monitored and controlled via memory mapped registers in the CPLD and the two FPGAs. These registers are accessed using the Uniboard Control Protocol (UCP) over the 1GbE connection to each CPLD (provided via the subrack). This test overrides the memory map in every FPGA, then reads it back. This verifies that the 1GbE interface is working as expected in both directions, the CPLD can correctly decode instructions, and that the memory map interface between the CPLD and both FPGAs is working as expected. This test is executed for all tiles in a station.

Methodology

  1. For a single FPGA, generate a pattern of 2560 integers and write this to the FPGA memory map.

  2. Read this pattern back and verify it matches the written pattern. Steps 1 and 2 will then be repeated for 100 iterations.

  3. After rerunning steps 1 and 2 for 100 iterations for 100 patterns, repeat everything for the other FPGA in the TPM.

  4. Once all FPGAs in a TPM have been tested, repeat steps 1-3 for the next TPM until all TPMs are tested.

  5. Once all TPMs have been tested, the final step is to check for any errors.