DDR Test

Purpose

This test is intended to validate that the full contents of the DDR memory available on a given TPM can be written to and read back by the FPGA without error. This test is executed on all FPGAs, on all TPMs, simultaneously for a specified duration.

Methodology

1. All data transmission from a TPM is stopped and the signal chain is reset to give exclusive access of the DDR to the embedded test module.

2. The DDR is initialised and the DDR capacity of each board is read from EEPROM and used to determine the scope of the test.

3. The embedded test module in the FPGA firmware is started. This writes an incrementing pattern to every address in the DDR then reads it back.

4. The software continuously monitors the embedded test module’s error counter to determine if the test has encountered any errors. The test completes after the specified duration, or when it encounters errors.